In recent years, reversible circuits have drawn high attention due to their usability in power consumption optimization of low power CMOS circuits in addition to quantum computing. On the other hand, fault and error tolerance has been one of the vital characteristics of new circuits because of the increasing susceptibility of these circuits against environmental effects. As ADDER circuits are the main parts of processing and arithmetic circuits, in this paper, we first propose a new gate to design a parity-preserving full ADDER, and then, introduce two new fault-tolerant reversible BCD ADDERs. Based on performed comparisons between the proposed structures and the existing gates and ADDERs, the new full ADDER and BCD ADDERs are the best or favorable designs according to the number of required gates, hardware complexity, delay and quantum cost.

In this paper, an enhanced self-checking carry select ADDER (CSeA) architecture is introduced. However, we first show that the carry select ADDER design presented literature does not have the self-checking property in all of its parts in spite of the stated claim. Then, we present a corrected design with the self-checking property that requires more overheads. In addition, we reveal some mistakes in reporting the transistor count of the proposed design in the literature in different sizes, and correct them which again leads to more transistor count and overhead. At the end, due to the fact that the performance of a CSeA depends on its grouping structure, the area overheads of different CSeAs including the corrected designs and the best of previous self-checking designs will be evaluated with respect to the same-size and different-size grouping structures. These evaluations show the comparison of different CSeAs, more appropriate compared to the previous evaluations.

Differential Cascode Voltage Switch (DCVS) is one of the most well-known logic styles, which forms a robust structure. In addition, two complementary outputs are produced in this logic style at the same time. It has several unique attributes and different applications. This paper presents three comparable methods to design some ternary half ADDERs, whose efficiencies are superior especially when they are put one after another in a cascading scenario. These cells are essential for the realization of larger arithmetic circuits. In the third proposed method, instead of ternary inverters, which consume considerable static power, built-in low-power binary boosters are exploited to reinforce driving power of the DCVS circuits. Simulation results by HSPICE and 32 nm Carbon Nanotube Field Effect Transistor (CNFET) technology demonstrate that the new ADDER cell with binary boosters operates 21. 8% faster and consume 6. 7% less power than the cell with ternary inverters in a real test bed. Furthermore, the final design is compared with three other ternary half ADDERs. The new design is faster than all of them, and also consumes less power and energy than the previous DCVS half ADDER.